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WICED Smart™ v2.2.3 - API Reference Guide |  |
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WICED Smart™ v2.2.3 - API Reference Guide | |
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Define functions to access sync pulse driver. More...
Data Structures | |
| struct | syncp_chanConfig |
| Channel configuration info. More... | |
| struct | SyncedPulseConfig |
| Configuration info. More... | |
| struct | SyncedPulseControl |
| Control information that changes during operation (as opposed to configuration information that is read in at startup and does not change) More... | |
| struct | SyncedPulseState |
| The internal runtime state of the synced pulse driver. More... | |
Macros | |
| #define | NUM_SYNCED_PULSE_HW_CHANS 4 |
| Number of synced pulse channels hardware supports. | |
Enumerations | |
| enum | { HW_LHL_OPTCTL_IR_SRC_MASK = 0x0F00, HW_LHL_OPTCTL_IR_SRC_IR2_3V_ALT3 = 0x0F00, HW_LHL_OPTCTL_IR_SRC_IR2_3V_ALT2 = 0x0E00, HW_LHL_OPTCTL_IR_SRC_P15_ALT3 = 0x0D00, HW_LHL_OPTCTL_IR_SRC_IR1_3V_ALT1 = 0x0C00, HW_LHL_OPTCTL_IR_SRC_IR2_3V_ALT1 = 0x0B00, HW_LHL_OPTCTL_IR_SRC_IR2_3V = 0x0A00, HW_LHL_OPTCTL_IR_SRC_P15_ALT2 = 0x0900, HW_LHL_OPTCTL_IR_SRC_P0_ALT1 = 0x0800, HW_LHL_OPTCTL_IR_SRC_P39_ALT3 = 0x0700, HW_LHL_OPTCTL_IR_SRC_P39_ALT2 = 0x0600, HW_LHL_OPTCTL_IR_SRC_P15_ALT1 = 0x0500, HW_LHL_OPTCTL_IR_SRC_IR1_3V = 0x0400, HW_LHL_OPTCTL_IR_SRC_P39_ALT1 = 0x0300, HW_LHL_OPTCTL_IR_SRC_P39 = 0x0200, HW_LHL_OPTCTL_IR_SRC_P15 = 0x0100, HW_LHL_OPTCTL_IR_SRC_P0_0 = 0x0000 } |
| Synced pulse register definitions. | |
| enum | { HW_LPO_SEL_MAIN60HZ_CNT_READBACK_MASK = 0x0004, HW_LPO_SEL_MAIN60HZ_CNT_READBACK_ENABLE = 0x0004, HW_LPO_SEL_MAIN60HZ_CNT_READBACK_DISABLE = 0x0000, HW_LPO_SEL_TRIAC_OUTPUT_INVERT_ALL_MASK = 0x00F0, HW_LPO_SEL_TRIAC1_OUTPUT_INVERT_SHIFT = 4 } |
| enum | SyncedPulseOffState { SYNCED_PULSE_OFF_STATE_LOW = 0, SYNCED_PULSE_OFF_STATE_HIGH = 1, SYNCED_PULSE_CHAN_NOT_USED } |
| Defines a bt resyncable synced pulse driver class. More... | |
| enum | SyncedPulseTriggerMode { TRIGGER_MODE_BT_CLK, TRIGGER_MODE_INPUT_PORT } |
| Input trigger mode–either btclk or input port. | |
| enum | { HW_MIA_60HZ_CTL_MODE_BT_CLK_MASK = 0x0100, HW_MIA_60HZ_CTL_MODE_BT_CLK_ENABLE = 0x0100, HW_MIA_60HZ_CTL_MODE_BT_CLK_DISABLE = 0x0000, HW_MIA_60HZ_CTL_TRIAC4_MASK = 0x0080, HW_MIA_60HZ_CTL_TRIAC4_ENABLE = 0x0080, HW_MIA_60HZ_CTL_TRIAC4_DISABLE = 0x0000, HW_MIA_60HZ_CTL_TRIAC3_MASK = 0x0040, HW_MIA_60HZ_CTL_TRIAC3_ENABLE = 0x0040, HW_MIA_60HZ_CTL_TRIAC3_DISABLE = 0x0000, HW_MIA_60HZ_CTL_MODE_DIMMER_MASK = 0x0020, HW_MIA_60HZ_CTL_MODE_DIMMER_ENABLE = 0x0020, HW_MIA_60HZ_CTL_MODE_DIMMER_DISABLE = 0x0000, HW_MIA_60HZ_CTL_TRIAC2_MASK = 0x0018, HW_MIA_60HZ_CTL_TRIAC2_ENABLE = 0x0008, HW_MIA_60HZ_CTL_TRIAC2_DISABLE = 0x0000, HW_MIA_60HZ_CTL_TRIAC1_MASK = 0x0004, HW_MIA_60HZ_CTL_TRIAC1_ENABLE = 0x0004, HW_MIA_60HZ_CTL_TRIAC1_DISABLE = 0x0000, HW_MIA_60HZ_CTL_SRC_MASK = 0x0002, HW_MIA_60HZ_CTL_SRC_P6 = 0x0002, HW_MIA_60HZ_CTL_SC_OPT_CTL_IR_SRC = 0x0000, HW_MIA_60HZ_CTL_MODULE_MASK = 0x0001, HW_MIA_60HZ_CTL_MODULE_ENABLE = 0x0001, HW_MIA_60HZ_CTL_MODULE_DISABLE = 0x0000 } |
| main60hz_ctl_adr bit defines | |
| enum | { HIDDCFA_PCX_TO_NAT, HIDDCFA_NAT_TO_PCX } |
| enum | { BTCLK_VSYNC_VAL2_MASK = 0x1F, MAX_INTERVAL_THRESHOLD = 65535 } |
Functions | |
| void | syncp_init (SyncedPulseConfig *config) |
| void | syncp_enableInputPortTriggerMode (void) |
| void | syncp_enableBtClkTriggerMode (UINT32 intervalThreshold, UINT32 piconetIndex, UINT32 clk, UINT32 phaseCount) |
| void | syncp_disableModule (void) |
| void | syncp_enableChan (UINT32 chanNum, UINT32 onDelay, UINT32 offDelay) |
| void | syncp_disableChan (UINT32 chanNum) |
| void | syncp_setChanOnOffDelays (UINT32 chanNum, UINT32 onDelay, UINT32 offDelay) |
| void | syncp_getChanOnOffDelays (UINT32 chanNum, UINT32 *pOnDelay, UINT32 *pOffDelay) |
| BOOL32 | syncp_isChanControlEnabled (UINT32 chanNum) |
| BOOL32 | syncp_isChanCurrentlyEnabled (UINT32 chanNum) |
| BOOL32 | syncp_isModuleEnabled (void) |
| UINT32 | syncp_getCurrentIntervalCounter (void) |
| UINT32 | syncp_getIntervalThreshold (void) |
| SyncedPulseConfig * | syncp_getConfig (void) |
| void | syncp_setIntervalThreshold (UINT32 intervalThreshold) |
| void | syncp_btPiconetClkSync (UINT32 piconetIndex, UINT32 clk, UINT32 phaseCount) |
| void | syncp_btNativeClkSync (UINT32 piconetIndex, UINT32 clk, UINT32 phaseCount) |
| void | syncp_convertFutureBtClk (UINT32 piconetIndex, UINT32 *pFutureClk, UINT32 *pFuturePhaseCount, UINT32 direction) |
| void | syncp_updateChanState (UINT32 chanNum) |
| void | syncp_updateAllChanStates (void) |
| void | syncp_writeTargetSyncTime (UINT32 clk, UINT32 phaseCount) |
Variables | |
| SyncedPulseConfig | syncedPulseConfig |
Define functions to access sync pulse driver.
