290 lines
9.8 KiB
C
290 lines
9.8 KiB
C
/**
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* @file wm_hostspi.h
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*
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* @brief host spi Driver Module
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*
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* @author dave
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*
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* Copyright (c) 2015 Winner Microelectronics Co., Ltd.
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*/
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#ifndef WM_HOST_SPI_H
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#define WM_HOST_SPI_H
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#include "wm_type_def.h"
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#include "list.h"
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#include "wm_osal.h"
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#include "wm_ram_config.h"
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#define SPI_USE_DMA
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#define SPI_DMA_CMD_MAX_SIZE (0x20)
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#define SPI_DMA_BUF_MAX_SIZE (8160)
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#define SPI_DMA_MAX_TRANS_SIZE (4092)
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/**
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* error code.
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*/
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#define TLS_SPI_STATUS_OK (0)
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#define TLS_SPI_STATUS_EINVAL (-1)
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#define TLS_SPI_STATUS_ENOMEM (-2)
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#define TLS_SPI_STATUS_EBUSY (-3)
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#define TLS_SPI_STATUS_ESHUTDOWN (-4)
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#define TLS_SPI_STATUS_EPERM (-5)
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#define TLS_SPI_STATUS_ECLKNOSUPPORT (-6)
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#define TLS_SPI_STATUS_EMODENOSUPPORT (-7)
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#define SPI_MASTER_FIFO_SIZE (32)
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/**
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* the SPI master controller's configuration data.
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*/
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/** configuration data. */
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#define SPI_CPHA (0x01) /** clock phase. */
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#define SPI_CPOL (0x02) /** clock polarity. */
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#define TLS_SPI_MODE_0 (0|0) /** motorola mode. */
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#define TLS_SPI_MODE_1 (0|SPI_CPHA)
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#define TLS_SPI_MODE_2 (SPI_CPOL|0)
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#define TLS_SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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#define TLS_SPI_CS_LOW 0x00 /** chipselect active low. */
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#define TLS_SPI_CS_HIGH 0x01 /** chipselect active high. */
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#define TLS_SPI_FCLK_MIN (1000) /** minimum work clock rate(Hz). */
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#define TLS_SPI_FCLK_MAX (APB_CLK/2) /** maximum work clock rate(Hz). */
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/** default configuration data. */
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#define SPI_DEFAULT_SPEED (2000000) /** default clock rate is 2MHz. */
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#define SPI_DEFAULT_MODE (TLS_SPI_MODE_0) /** default mode MODE_0. */
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#define SPI_CS_ACTIVE_MODE (TLS_SPI_CS_LOW) /** default chipselect mode is active low. */
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#define SPI_CS_INACTIVE_MODE (TLS_SPI_CS_HIGH)
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/** SPI transaction message status. */
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#define SPI_MESSAGE_STATUS_IDLE (0)
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#define SPI_MESSAGE_STATUS_INPROGRESS (1)
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#define SPI_MESSAGE_STATUS_DONE (2)
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/**slave type*/
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#define SPI_SLAVE_FLASH 0 /**flash */
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#define SPI_SLAVE_CARD 1 /** SD card */
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#define SPI_SLAVE_CONTROL_PIN 0
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/**transfer type*/
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#define SPI_BYTE_TRANSFER 0 /**byte transfer*/
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#define SPI_WORD_TRANSFER 1 /**word transfer*/
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#define SPI_DMA_TRANSFER 2 /** DMA transfer */
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/**
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* a read/write buffer pair
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*
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* SPI transfers always write the same number of bytes as they read.
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* If the transmit buffer is null, zeroes will be shifted out while
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* filling rx_buf. If the receive buffer is null, the data shifted in
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* will be discarded.
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*/
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struct tls_spi_transfer
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{
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struct dl_list transfer_list; /**< transfers are sequenced through
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tls_spi_message.transfers. */
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const void *tx_buf; /**< data to be written, or NULL. */
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void *rx_buf; /**< data to be read, or NULL. */
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u32 len; /**< size of rx and tx buffers (in bytes). */
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u32 delay_usecs; /**< microseconds to delay after this transfer. */
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};
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/**
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* one multi-segment SPI transaction
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*
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* A struct tls_spi_message is used to execute an atomic sequence of data
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* transfers, each represented by a struct tls_spi_transfer. The sequence
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* is "atomic" in the sense that no other spi_message may use that SPI bus
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* until that sequence completes.
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*/
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struct tls_spi_message
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{
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struct dl_list queue; /**< transaction messages are sequenced through
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tls_spi_port.wait_queue. */
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struct dl_list transfers; /**< list of transfer segments in this transaction. */
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void (*complete) (void *); /**< called to report transaction completions. */
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void *context; /**< the argument to complete() when it's called. */
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u32 status; /**< transaction message status. */
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};
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/**
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* driver structure to SPI master controller
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*
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* This data structure presents the SPI master controller's configuration
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* data. The device attached to this SPI master controller share the same
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* transfer mode, chipselect mode and clock rate. And this structure maintains
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* a queue of tls_spi_message transactions and uses this tls_spi_message transaction
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* to access to the SPI device. For each such message it queues, it calls the message's
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* completion function when the transaction completes.
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*/
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struct tls_spi_port
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{
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u32 speed_hz; /**< clock rate to be used. */
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u8 cs_active; /**< chipselect mode, maybe active low or active
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high. */
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u8 mode; /**< SPI transfer mode: mode_0(CPHA=0, CHOL=0),
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mode_1(CPHA=0, CHOL=1), mode_2(CPHA=1,
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CHOL=0), mode_3(CPHA=1, CHOL=1). */
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u8 reconfig;
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struct dl_list wait_queue; /**< wait list of transaction messages. */
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tls_os_queue_t *lock;
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tls_os_queue_t *msg_queue; /**< notify the schedule thread that there's
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transaction message queued. */
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struct tls_spi_message *current_message; /**< current transaction message
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in-progressing. */
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u32 current_remaining_transfer; /**< remaining transfer segments count in
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current transaction message. */
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struct tls_spi_transfer *current_transfer; /**< current transfer segment
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in-progressing. */
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u32 current_remaining_bytes; /**< remaining data length in current
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transfer segment. */
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u8 transtype; /**< transfer type */
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};
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/**
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* @defgroup Driver_APIs Driver APIs
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* @brief Driver APIs
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*/
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/**
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* @addtogroup Driver_APIs
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* @{
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*/
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/**
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* @defgroup MASTERSPI_Driver_APIs MASTER SPI Driver APIs
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* @brief MASTERSPI driver APIs
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*/
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/**
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* @addtogroup MASTERSPI_Driver_APIs
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* @{
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*/
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/**
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* @brief This function is used to initialize the SPI master driver.
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*
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* @param[in] None
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*
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* @retval TLS_SPI_STATUS_OK if initialize success
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* @retval TLS_SPI_STATUS_EBUSY if SPI is already initialized
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* @retval TLS_SPI_STATUS_ENOMEM if malloc SPI memory fail
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*
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* @note None
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*/
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int tls_spi_init(void);
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/**
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* @brief This function is used to setup the spi controller.
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*
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* @param[in] mode is CPOL and CPHA type defined in TLS_SPI_MODE_0 to TLS_SPI_MODE_3
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* @param[in] cs_active is cs mode, defined as TLS_SPI_CS_LOW or TLS_SPI_CS_HIGH
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* @param[in] fclk is spi clock,the unit is HZ.
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*
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* @retval TLS_SPI_STATUS_OK if setup success
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* @retval TLS_SPI_STATUS_EMODENOSUPPORT if mode is not support
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* @retval TLS_SPI_STATUS_EINVAL if cs_active is not support
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* @retval TLS_SPI_STATUS_ECLKNOSUPPORT if fclk is not support
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*
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* @note None
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*/
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int tls_spi_setup(u8 mode, u8 cs_active, u32 fclk);
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/**
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* @brief This function is used to synchronous write data by SPI.
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*
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* @param[in] buf data to be sent.
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* @param[in] len data length.
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*
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* @retval TLS_SPI_STATUS_OK if write success.
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* @retval TLS_SPI_STATUS_EINVAL if argument is invalid.
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* @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory.
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* @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed.
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*
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* @note None
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*/
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int tls_spi_write(const u8 * buf, u32 len);
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/**
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* @brief This function is used to synchronously read data from SPI.
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*
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* @param[in] buf is the buffer for saving SPI data.
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* @param[in] len is the data length.
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*
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* @retval TLS_SPI_STATUS_OK if write success.
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* @retval TLS_SPI_STATUS_EINVAL if argument is invalid.
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* @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory.
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* @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed.
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*
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* @note None
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*/
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int tls_spi_read(u8 * buf, u32 len);
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/**
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* @brief This function is used to synchronously write command and then read data from SPI.
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*
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* @param[in] txbuf is the write data buffer.
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* @param[in] n_tx is the write data length.
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* @param[in] rxbuf is the read data buffer.
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* @param[in] n_rx is the read data length.
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*
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* @retval TLS_SPI_STATUS_OK if write success.
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* @retval TLS_SPI_STATUS_EINVAL if argument is invalid.
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* @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory.
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* @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver has not been installed.
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*
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* @note None
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*/
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int tls_spi_read_with_cmd(const u8 * txbuf, u32 n_tx, u8 * rxbuf, u32 n_rx);
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/**
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* @brief This function is used to synchronous write 32bit command then write data from SPI.
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*
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* @param[in] cmd is the command data.
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* @param[in] n_cmd is the command len,can not bigger than four
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* @param[in] txbuf is the write data buffer.
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* @param[in] n_tx is the write data length.
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*
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* @retval TLS_SPI_STATUS_OK if write success.
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* @retval TLS_SPI_STATUS_EINVAL if argument is invalid.
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* @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory.
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* @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed.
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*
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* @note None
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*/
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int tls_spi_write_with_cmd(const u8 * cmd, u32 n_cmd, const u8 * txbuf, u32 n_tx);
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/**
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* @brief This function is used to set SPI transfer mode.
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*
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* @param[in] type is the transfer type.
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* SPI_BYTE_TRANSFER ->byte transfer;
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* SPI_WORD_TRANSFER ->word transfer;
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* SPI_DMA_TRANSFER ->DMA transfer;
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*
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* @return None
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*
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* @note None
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*/
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void tls_spi_trans_type(u8 type);
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* WM_HOST_SPI_H */
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