Small correction to the schematic, started PCB routing and exported schematic in pdf format for quick viewing
This commit is contained in:
parent
b13c2d5459
commit
8f26466cc4
@ -12,6 +12,22 @@
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 53cf90ed-75fa-4692-8479-951cbed69bdd)
|
||||
)
|
||||
(fp_text user "-" (at 2 3 unlocked) (layer "F.SilkS")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 05b6e6b8-4ffa-4cfb-be82-c87d6ea34ae1)
|
||||
)
|
||||
(fp_text user "+" (at 2 -3 unlocked) (layer "F.SilkS")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 2ba0384e-0b14-4d2c-a9fa-8a4c7313b13b)
|
||||
)
|
||||
(fp_text user "D-" (at 3 -1 unlocked) (layer "F.SilkS")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp d83ed1cf-18e9-48eb-85b0-7e681c902430)
|
||||
)
|
||||
(fp_text user "D+" (at 3 1 unlocked) (layer "F.SilkS")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp ec816e92-34db-42c2-aa73-905eb31b2716)
|
||||
)
|
||||
(fp_line (start -1 -4) (end 1 -4) (layer "F.SilkS") (width 0.12) (tstamp 2de97e2b-e959-48cb-aa49-7c757d7a4539))
|
||||
(fp_line (start 1 4) (end -1 4) (layer "F.SilkS") (width 0.12) (tstamp b46339cc-0ad1-4122-8cd5-5ea02867ec5b))
|
||||
(fp_line (start -1 4) (end -1 -4) (layer "F.SilkS") (width 0.12) (tstamp d14cd274-8381-4cc4-84c6-1c62c2ef5db4))
|
||||
|
@ -24,6 +24,7 @@
|
||||
(fp_line (start 5.4 4.095) (end 5.4 2.355) (layer "F.SilkS") (width 0.12) (tstamp baf29ab7-1c2a-4630-95c9-bfc5a9c69e36))
|
||||
(fp_line (start -3.91 -1.3) (end -3.91 -2.5) (layer "F.SilkS") (width 0.12) (tstamp c72f4cef-5717-4ed7-ac29-574476807f2c))
|
||||
(fp_line (start -5.4 4.1) (end 5.4 4.1) (layer "F.SilkS") (width 0.12) (tstamp da04693d-1955-454a-a747-ec59ced6f776))
|
||||
(fp_circle (center 4.655 -2) (end 4.78 -2) (layer "F.SilkS") (width 0.25) (fill none) (tstamp e3b1b827-0fe1-4329-ac8b-2f9ae1dd9632))
|
||||
(fp_line (start -6.8 4.9) (end 6.8 4.9) (layer "F.CrtYd") (width 0.05) (tstamp 0d473d5b-04ab-41c2-a2c6-0997d4da58e3))
|
||||
(fp_line (start 6.8 -3) (end -6.8 -3) (layer "F.CrtYd") (width 0.05) (tstamp 34f5c3dd-4c6a-4940-b82e-589d7643c815))
|
||||
(fp_line (start 6.8 4.9) (end 6.8 -3) (layer "F.CrtYd") (width 0.05) (tstamp a235d6c1-a18a-425e-9210-aa79faffd5c3))
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
|
||||
{
|
||||
"board": {
|
||||
"active_layer": 44,
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "All Layers",
|
||||
"auto_track_width": true,
|
||||
"hidden_nets": [],
|
||||
@ -36,7 +36,6 @@
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
|
@ -37,7 +37,7 @@
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.15,
|
||||
"silk_line_width": 0.153,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
@ -48,7 +48,13 @@
|
||||
"min_clearance": 0.0
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"diff_pair_dimensions": [
|
||||
{
|
||||
"gap": 0.0,
|
||||
"via_gap": 0.0,
|
||||
"width": 0.0
|
||||
}
|
||||
],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
@ -97,23 +103,41 @@
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_clearance": 0.127,
|
||||
"min_copper_edge_clearance": 0.0,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_clearance": 0.254,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_track_width": 0.127,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"min_via_diameter": 0.5,
|
||||
"solder_mask_clearance": 0.0,
|
||||
"solder_mask_min_width": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [],
|
||||
"via_dimensions": [],
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.127,
|
||||
0.25,
|
||||
0.76,
|
||||
1.27,
|
||||
2.03,
|
||||
2.79,
|
||||
3.81,
|
||||
4.57,
|
||||
5.59,
|
||||
6.6,
|
||||
7.62
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
@ -404,7 +428,7 @@
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"plot_directory": "./",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
|
File diff suppressed because it is too large
Load Diff
BIN
design/Kicad/W800_Smart_Watch/W800_Smart_Watch.pdf
Normal file
BIN
design/Kicad/W800_Smart_Watch/W800_Smart_Watch.pdf
Normal file
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user